1. Field of the Invention
The present invention relates to a data processing device for a super-scalar-type or VLIW-type RISC type processor which can simultaneously execute a plurality of instructions, with one instruction made up of at least one word of data or more, and, in particular, to a data processing device in which different types of data are stored in an external memory other than that of the data which is to be executed on by the processor.
2. Description of the Prior Art
There is no uniform standard method for affixing an address to data in byte (8-bit) units for data used in a computer system. At the present time two types of systems exist. As shown in FIG. 1A, one system is the big-endian-type in which the addresses are increased, in sequence, from the byte on the Most Significant Bit (MSB) side, and, conversely, the other system is the little-endian-type in which the addresses are increased in sequence from the byte on the Least Significant Bit (LSB) side.
For this reason when the data is accessed in byte units, the order of input of byte data for the two methods is opposite and problems are produced during data exchange with respect to compatibility.
On the other hand, a recent trend has been toward a processor, as the mainstream, in which a plurality of instructions can be executed simultaneously at high speed in one cycle, using both a super-scalar system and a VLIW system in an RISC processor.
These processors are provided with a wide bus so that large amounts of data can be transmitted at one time (for example, a width of four words, which would be 128 bits) even when the data is exchanged between the processor and an external memory. In addition, a large number of connector pins are provided for the external memory. For example, in the case of a processor which can accommodate four words (128 bits; one word=32 bits) at one time from an external memory, data written in by the big-endian type or the little-endian type is recorded with an external memory 11, in the order as shown in FIG. 1B. This data passes through the connector pins and is input in the sequence shown in FIG. 1C.
Specifically, the data is written in from the four groups of connector pins A, B, C, D (one group comprises 32 connector pins, specifically 32 bits) in the sequence shown in the drawing. The internal hardware of a conventional processor 13 is constructed to process data produced in either the big-endian type or the little-endian type, so that when accessing data of a different form the following two problems exist. The first problem stems from the reversal of the sequence for each individual piece of data of byte units within one word (32 bits).
The second problem is the point that the sequence of four words of data is reversed. In order to cope with data drawn up in the two types--the big-endian--and the little-endian-types--a switching circuit 14 for data of byte units made up of a selector (SEL), as shown in FIG. 2, is necessary to handle the problem of reversal of the byte sequence. Even when this circuit 14 is provided, the second problem still remains when data of word units drawn up by the big-endian and the little-endian types is read in through the connector pins A to D as a result of the reversal of the sequence of the words for both types, as shown in FIG. 1C. Specifically, the problem of the reversal of the sequence of the words exists.
As shown in FIG. 3, in the case of a processor of the super-scalar-type or the like, a plurality of instructions in word units is simultaneously read in from the external memory and introduced into an instruction register 12 provided in a processor chip 18. As stated above, the internal hardware of the processor chip 13 is set and formed in accordance with either the big-endian-type or the little-endian-type. For this reason, the sequence of input instructions in word units ends up reversed for data drawn up by the different endian types. Accordingly, the correct control of calculation and processing by means of the processor 13 is impossible.
In order to avoid this, a method for exchanging data has been considered, as shown in FIG. 4, in which a SEL 15 (selector) is newly provided inside the processor immediately before the instruction register 12, in addition to the switching circuit 14 shown in FIG. 2. This selector is for switching the order of the words. However, because the above-mentioned byte switching circuit 14 must also be provided, the size of the chip is considerably increased in comparison with the data bus width, because of the bus wiring, namely the configuration of the circuit and the like is increased in practice.
Even when the selector 15 shown in FIG. 4 is provided, the following problems remain. For example, when double precision floating point data is handled, double precision data with a format of two words in series, as shown in FIG. 5A, ends up with a format as shown in FIG. 5B when changed by each word unit. In FIG. 5A and 5B, an s indicates the sign, an e the exponent, and an f the mantissa of the data.
In this manner, a conventional data processing device must reverse the order of the data in each byte unit for data formed by means of an endian type which differs from the endian type which the device is capable of processing, and, in particular, the order of each word unit of an instruction is reversed so that operational control becomes impossible. Another drawback is that, in the case of operation using data of two or more words in series, the data format is broken Up and rearranged into a format which cannot be utilized.